PavanKalyan Jagarlamudi

PavanKalyan Jagarlamudi

Hardware Chip Design EngineerIndia
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PavanKalyan Jagarlamudi

PavanKalyan Jagarlamudi

Hardware Chip Design EngineerIndia
Work history
    S
    S
    Trainee VLSI Physical Design EngineerSemicon Techno Labs
     - Bengaluru, IndiaFreelance
    The process of transforming a circuit description into the physical layout design. Backend Physical development of Chip. Floorplan, Placement, CTS and Routing. Experienced in using Cadence encounter tool.
Education
    N
    N
    B.TechNRI Institue of Technolog
     - India